5.1.4 PLL Clock – clkPLL
The PLL clock allows the fast peripherals to be clocked directly from a 64/32MHz clock. A 16MHz clock is also derived for
the CPU.
5.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
5.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as illustrated in Table 5-1. The clock from
the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 5-1. Device Clocking Options Select(1)
System
Device Clocking Option
Clock
PLL Input
CKSEL3..0
External crystal/ceramic resonator
Ext Osc
RC Osc
1111 - 1000
PLL output divided by 4: 16MHz / PLL driven by external
crystal/ceramic resonator
Ext Osc
PLL / 4
Ext Osc
Ext Osc
0100
0101
PLL output divided by 4: 16MHz / PLL driven by external
crystal/ceramic resonator
Reserved
N/A
N/A
0110
0111
0011
0010
0001
0000
Reserved
N/A
N/A
PLL output divided by 4: 16MHz
Calibrated internal RC oscillator
PLL output divided by 4: 16MHz/PLL driven by external clock
External clock
PLL / 4
RC Osc
PLL / 4
Ext Clk
RC Osc
RC Osc
Ext Clk
RC Osc
Notes: 1. For all fuses “1” means unprogrammed while “0” means programmed.
2. Ext Osc: External oscillator
3. RC Osc: Internal RC oscillator
4. Ext Clk: External clock input
The various choices for each clocking option is given in the following sections. When the CPU wakes up from power-down or
power-save, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction
execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level
before starting normal operation. The watchdog oscillator is used for timing this real-time part of the start-up time. The
number of WDT oscillator cycles used for each time-out is shown in Table 5-2 on page 26. The frequency of the Watchdog
Oscillator is voltage dependent as shown in Section 27-31 “Watchdog Oscillator Frequency versus VCC” on page 294.
Table 5-2. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)
Typ Time-out (VCC = 3.0V)
Number of Cycles
4K (4,096)
4.1ms
65ms
4.3ms
69ms
64K (65,536)
26
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
