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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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Caution:  
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM master write  
enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access,  
the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is  
recommended to have the global interrupt flag cleared during all the steps to avoid these problems.  
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this  
bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles  
before the next instruction is executed.  
• Bit 0 – EERE: EEPROM Read Enable  
The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR  
register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one  
instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles  
before the next instruction is executed.  
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible  
to read the EEPROM, nor to change the EEAR register.  
The calibrated oscillator is used to time the EEPROM accesses. Table 4-2 lists the typical programming time for EEPROM  
access from the CPU.  
Table 4-2. EEPROM Programming Time.  
Symbol  
Number of Calibrated RC Oscillator Cycles  
Typ Programming Time  
EEPROM write (from  
CPU)  
26368  
3.3 ms  
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume  
that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these  
functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the  
EEPROM write function must also wait for any ongoing SPM command to finish.  
Assembly Code Example  
EEPROM_write:  
; Wait for completion of previous write  
sbic  
rjmp  
EECR,EEWE  
EEPROM_write  
; Set up address (r18:r17) in address register  
out  
out  
EEARH, r18  
EEARL, r17  
; Write data (r16) to data register  
out EEDR,r16  
; Write logical one to EEMWE  
sbi EECR,EEMWE  
; Start eeprom write by setting EEWE  
sbi  
ret  
EECR,EEWE  
C Code Example  
void EEPROM_write (unsigned int uiAddress, unsigned char ucData)  
{
/* Wait for completion of previous write */  
while(EECR & (1<<EEWE))  
;
/* Set up address and data registers */  
EEAR = uiAddress;  
EEDR = ucData;  
/* Write logical one to EEMWE */  
EECR |= (1<<EEMWE);  
/* Start eeprom write by setting EEWE */  
EECR |= (1<<EEWE);  
}
22  
ATmega16/32/64/M1/C1 [DATASHEET]  
7647O–AVR–01/15  
 
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