4.3.4 The EEPROM Control Register – EECR
Bit
7
–
6
–
5
4
3
2
1
0
EERE
R/W
0
EEPM1 EEPM0 EERIE EEMWE EEWE
EECR
Read/Write
Initial Value
R
0
R
0
R/W
X
R/W
X
R/W
0
R/W
0
R/W
X
• Bits 7..6 – Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
• Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE. It
is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase
and Write operations in two different operations. The Programming times for the different modes are shown in Table 4-1.
While EEWE is set, any write to EEPMn will be ignored. during reset, the EEPMn bits will be reset to 0b00 unless the
EEPROM is busy programming.
Table 4-1. EEPROM Mode Bits
EEPM1
EEPM0
Programming Time
Operation
0
0
1
1
0
1
0
1
3.4ms
1.8ms
1.8ms
–
Erase and write in one operation (atomic operation)
Erase only
Write only
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the
interrupt. The EEPROM ready interrupt generates a constant interrupt when EEWE is cleared. The interrupt will not be
generated during EEPROM write or SPM.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting
EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will
have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up,
the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a
logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when
writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory control and status regis-
ter) becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash
programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot
Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
Section 24. “Boot Loader Support – Read-while-write Self-Programming ATmega16/32/64/M1/C1” on page 241 for details
about Boot programming.
ATmega16/32/64/M1/C1 [DATASHEET]
21
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
