The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 1024/2048/4096 bytes of
internal data SRAM in the Atmel® ATmega16/32/64/M1/C1 are all accessible through all these addressing modes. The
register file is described in Section 3.5 “General Purpose Register File” on page 13.
Figure 4-2. Data Memory Map for 1024/2048/4096 Internal SRAM
Data Memory
32 Registers
64 I/O Registers
0x0000 - 0x001F
0x0020 - 0x005F
160 Ext I/O Registers 0x0060 - 0x00FF
0x0100
Internal SRAM
(1024x8)
(2048x8)
0x04FF/0x08FF/0x10FF
(4096x8)
4.2.1 SRAM Data Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clkCPU cycles as described in Figure 4-3 on page 19.
Figure 4-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Data
Compute Address
Address valid
Write
Read
WR
Data
RD
Memory Access Instruction
Next Instruction
ATmega16/32/64/M1/C1 [DATASHEET]
19
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
