4.3
EEPROM Data Memory
The Atmel® ATmega16/32/64/M1/C1 contains 512/1024/2048 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address
Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see Section 25.9 “Serial Downloading” on
page 270, and Section 25.6 “Parallel Programming Parameters, Pin Mapping, and Commands” on page 259 respectively.
4.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 4-2. A self-timing function, however, lets the user software detect
when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for
some period of time to run at a voltage lower than specified as minimum for the clock frequency used. Section 4.3.5
“Preventing EEPROM Corruption” on page 23 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
4.3.2 The EEPROM Address Registers – EEARH and EEARL
Bit
15
14
13
12
11
10
9
8
–
–
–
–
–
EEAR10 EEAR9 EEAR8
EEARH
EEARL
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0
7
R
6
R
5
R
4
R
3
R
2
R/W
R/W
X
1
R/W
R/W
X
0
R/W
R/W
X
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
X
X
X
X
X
X
X
X
• Bits 15.11 – Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
• Bits 9..0 – EEAR10..0: EEPROM Address
The EEPROM address registers – EEARH and EEARL specify the EEPROM address in the 512/1024/2048 bytes EEPROM
space. The EEPROM data bytes are addressed linearly between 0 and 511/1023/2047. The initial value of EEAR is
undefined. A proper value must be written before the EEPROM may be accessed.
4.3.3 The EEPROM Data Register – EEDR
Bit
7
6
5
4
3
2
1
0
EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0
EEDR
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by
the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address
given by EEAR.
20
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
