17.6.2 LIN Status and Interrupt Register - LINSIR
Bit
7
6
5
4
3
2
1
0
LIDST2
LIDST1
LIDST0
LBUSY
LERR
R/Wone
0
LIDOK
R/Wone
0
LTXOK
R/Wone
0
LRXOK
R/Wone
0
LINSIR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bits 7:5 - LIDST[2:0]: Identifier Status
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●
●
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0xx = no specific identifier,
100 = Identifier 60 (0x3C),
101 = Identifier 61 (0x3D),
110 = Identifier 62 (0x3E),
111 = Identifier 63 (0x3F).
• Bit 4 - LBUSY: Busy Signal
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●
0 = Not busy,
1 = Busy (receiving or transmitting).
• Bit 3 - LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR - is set
in LINENIR.
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●
0 = No error,
1 = An error has occurred.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits. In
UART mode, this bit is also cleared by reading LINDAT.
• Bit 2 - LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
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0 = No identifier,
1 = Slave task: Identifier present, master task: Tx header complete.
The user clears this bit by writing 1, in order to reset this interrupt.
• Bit 1 - LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
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●
0 = No Tx,
1 = Tx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
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●
0 = No Rx
1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
192
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
