17.5.14 Message Filtering
Message filtering based upon the whole identifier is not implemented. Only a status for frame headers having 0x3C, 0x3D,
0x3E and 0x3F as identifier is available in the LINSIR register.
Table 17-4. Frame Status
LIDST[2..0]
0xx b
Frame Status
No specific identifier
60 (0x3C) identifier
61 (0x3D) identifier
62 (0x3E) identifier
63 (0x3F) identifier
100 b
101 b
110 b
111 b
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic checksum (sum over
the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this expected
checksum (the insertion of the ID field in the computation of the CRC is set - or not - just after entering the Rx or Tx response
command).
17.5.15 Data Management
17.5.15.1 LIN FIFO Data Buffer
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer accessible). This FIFO is
accessed via the LINDX[2..0] field of LINSEL register through the LINDAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can be read or written. The data
index is automatically incremented after each LINDAT access if the LAINC (active low) bit is cleared. A roll-over is
implemented, after data index=7 it is data index=0. Otherwise, if LAINC bit is set, the data index needs to be written
(updated) before each LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1, and so on. Nevertheless,
LINSEL must be initialized by the user before use.
17.5.15.2 UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data out and in read
access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
17.5.16 OCD Support
This section describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O view behavior in AVR Studio®)
1. LINCR:
- LINCR[6..0] are R/W accessible,
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
2. LINSIR:
- LIDST[2..0] and LBUSY are always Read accessible,
- LERR and LxxOK bit are directly accessible (unlike in execution, set or cleared directly by writing 1 or 0).
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR bits.
3. LINENR:
- All bits are R/W accessible.
4. LINERR:
- All bits are R/W accessible,
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
5. LINBTR:
- LBT[5..0] are R/W access only if LDISR is set,
- If LDISR is reset, LBT[5..0] are unchangeable.
ATmega16/32/64/M1/C1 [DATASHEET]
189
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
