• Bit 3 - LSERR: Synchronization Error Flag
●
●
0 = No error,
1 = Synchronization error. This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 2 - LPERR: Parity Error Flag
●
●
0 = No error,
1 = Parity error. This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 1 - LCERR: Checksum Error Flag
●
●
0 = No error,
1 = Checksum error. This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 0 - LBERR: Bit Error Flag
●
●
0 = no error,
1 = Bit error. This bit is cleared when LERR bit in LINSIR is cleared.
17.6.5 LIN Bit Timing Register - LINBTR
Bit
7
LDISR
R/W
0
6
-
5
4
3
2
1
0
LBT5
R/(W)
1
LBT4
R/(W)
0
LBT3
R/(W)
0
LBT2
R/(W)
0
LBT1
R/(W)
0
LBT0
R/(W)
0
LINBTR
Read/Write
Initial Value
R
0
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
●
●
0 = Bit timing re-synchronization enabled (default),
1 = Bit timing re-synchronization disabled.
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
Gives the number of samples of a bit.
sample-time = (1 / fclki/o ) x (LDIV[11..0] + 1)
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
17.6.6 LIN Baud Rate Register - LINBRR
Bit
7
LDIV7
-
6
LDIV6
-
5
LDIV5
-
4
LDIV4
-
3
LDIV3
LDIV11
11
2
LDIV2
LDIV10
10
1
LDIV1
LDIV9
9
0
LDIV0
LDIV8
8
LINBRRL
LINBRRH
Bit
15
14
13
12
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 15:12 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LIN-
BRR is written.
• Bits 11:0 - LDIV[11:0]: Scaling of clki/o Frequency
The LDIV value is used to scale the entering clki/o frequency to achieve appropriate LIN or UART baud rate.
194
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
