6. LINBRRH and LINBRRL:
- All bits are R/W accessible.
7. LINDLR:
- All bits are R/W accessible.
8. LINIDR:
- LID[5..0] are R/W accessible,
- LP[1..0] are Read accessible and are always updated on the fly.
9. LINSEL:
- All bits are R/W accessible.
10. LINDAT:
- All bits are in R/W accessible,
- Note that LAINC has no more effect on the auto-incrementation and the access to the full FIFO is done setting
LINDX[2..0] of LINSEL.
Note:
When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-
out) and further communication may be corrupted.
17.6 LIN / UART Register Description
Table 17-5. LIN/UART Register Bits Summary
Name
Bit 7
Bit 6
Bit 5
LCONF1
R/W
Bit 4
LCONF0
R/W
LBUSY
R
Bit 3
Bit 2
LCMD2
R/W
Bit 1
LCMD1
R/W
Bit 0
LCMD0
R/W
LSWRES
LIN13
LENA
LINCR
0
R/W
LIDST2
R
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
LERR
R/Wone
0
0
0
0
0
0
LIDST1
LIDST0
R
LIDOK
R/Wone
LTXOK
R/Wone
LRXOK
R/Wone
LINSIR
LINENIR
LINERR
LINBTR
LINBRRL
LINBRRH
LINDLR
LINIDR
0
0
0
0
0
0
0
1
0
0
R
—
—
—
—
LENERR
R/W
LENIDOK
LENTXOK
LENRXOK
R
R
LTOERR
R
R
R
0
R/W
LPERR
R
0
R/W
LCERR
R
0
R/W
LBERR
R
LABORT
R
LOVERR
R
LFERR
R
LSERR
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LDISR
R/W
LDIV7
R/W
—
LBT5
R/(W)
LDIV5
R/W
LBT4
R/(W)
LDIV4
R/W
—
LBT3
R/(W)
LDIV3
R/W
LBT2
R/(W)
LDIV2
R/W
LBT1
R/(W)
LDIV1
R/W
LBT0
R/(W)
LDIV0
R/W
R
LDIV6
R/W
—
—
LDIV11
R/W
LDIV10
R/W
LDIV9
R/W
LDIV8
R/W
R
R
R
R
LTXDL3
R/W
LP1
R
LTXDL2
R/W
LP0
R
LTXDL1
R/W
LTXDL0
R/W
LRXDL3
R/W
LRXDL2
R/W
LRXDL1
R/W
LRXDL0
R/W
LID5/LDL1
R/W
LID4/LDL0
R/W
LID3
LID2
LID1
LID0
0
0
R/W
R/W
R/W
R/W
—
—
—
—
LAINC
R/W
LINDX2
R/W
LINDX1
R/W
LINDX0
R/W
LINSEL
LINDAT
R
R
0
0
R
LDATA5
R/W
0
0
R
LDATA4
R/W
LDATA7
R/W
LDATA6
R/W
LDATA3
R/W
LDATA2
R/W
LDATA1
R/W
LDATA0
R/W
190
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
