14.6.1 Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK configuration bit, the
new whole set of values can be taken into account after the end of the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will be done at the end of
the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L, POCRnRAH/L, POCRnSBH/L
and POCRnRBH/L.
See these register’s description starting on in Section 14.16.7 “PSC Configuration Register – PCNF” on page 130
14.7 Overlap Protection
Thanks to overlap protection two outputs on a same module cannot be active at the same time. So it cannot generate cross
conduction. This feature can be disactivated thanks to POVEn (PSC overlap enable).
For ATmega16/64M1, and ATmega32M1 since rev C, the overlap protection is activated with only one condition:
1. POVENn=0 (PSC module n overlap enable)
Up to rev B of ATmega32M1, the overlap protection was activated with the 2 following conditions:
2. POVENn=0 (PSC module n overlap enable)
3. The two channels A and B of a pwm pair n must be activated (POENnA = POENnB = 1)
This difference can induce some behavior change between rev B and rev C of ATmega32M1, when only one channel of a
PWM pair output is active.
To avoid such behavior, it is recommended in case of using only one channel of a pwm pair, to disable overlap protection bit
(POVENn = 1).
14.8 Signal Description
Figure 14-9. PSC External Block View
CLK
PLL
CLK
I/O
12
12
12
12
12
12
12
12
12
12
POCRRB[11:0]
POCR0SB[11:0]
POCR0RA[11:0]
POCR0SA[11:0]
POCR1SB[11:0]
POCR1RA[11:0]
POCR1SA[11:0]
POCR2SB[11:0]
POCR2RA[11:0]
POCR2SA[11:0]
PSCOUT0A
PSCOUT0B
PSCOUT1A
PSCOUT1B
PSCOUT2A
PSCOUT2B
AC2O
AC1O
AC0O
PSCIN2
PSCIN1
PSCIN0
IRQPSC
PSCASY
122
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
