On-time 0 = 2 POCRnSAH/L 1/Fclkpsc
On-time 1 = 2 (POCRnRBH/L – POCRnSBH/L + 1) 1/Fclkpsc
Dead-time = (POCRnSBH/L – POCRnSAH/L) 1/Fclkpsc
PSC cycle = 2 (POCRnRBH/L + 1) 1/Fclkpsc
Minimal value for PSC cycle = 2 1/Fclkpsc
Note that in center aligned mode, POCRnRAH/L is not required (as it is in one-ramp mode) to control PSC Output waveform
timing. This allows POCRnRAH/L to be freely used to adjust ADC synchronization (See Section 14.12 “Analog
Synchronization” on page 126).
Figure 14-7. Controlled Start and Stop Mechanism in Centered Mode
POCRnRB
POCRnSB
POCRnSA
PSC Counter
Run
PSCOUTnA
PSCOUTnB
Note:
See Section 14.16.8 “PSC Control Register – PCTL” on page 130 (PCCYC = 1)
14.6 Update of Values
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are
updated at the same time at the end of the cycle by the PSC. The new set of values is calculated by software and the update
is initiated by software.
Figure 14-8. Update at the End of Complete PSC Cycle
Regulation Loop
Calculation
Writting in
PSC Registers
Request for
an Update
Software
Cycle
with Set i
Cycle
with Set i
Cycle
with Set i
Cycle
with Set i
PSC
Cycle
with Set j
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSC cycle.
ATmega16/32/64/M1/C1 [DATASHEET]
121
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
