W3H32M64EA-XSBX
ADVANCED
on and off, assuming ODT has been enabled via bits E2 and E6 of
the EMR. The ODT feature and ODT input ball are only used during
active, active power-down (both fast-exit and slow-exit modes), and
precharge power-down modes of operation. ODT must be turned
off prior to entering self refresh. During power-up and initialization
of the DDR2 SDRAM, ODT should be disabled until issuing the
EMR command to enable the ODT feature, at which point the ODT
ball will determine the RTT(EFF) value. Any time the EMR enables
the ODT function, ODT may not be driven HIGH until eight clocks
after the EMR has been enabled. See “ODT Timing” section for
ODT timing diagrams.
via the LM command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
EMR2 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions beyond
those controlled by the mode register. Currently, all bits in EMR3
are reserved, as shown in Figure 9. The EMR3 is programmed
via the LM command and will retain the stored information until it
is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in
Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an inverseAL of 0, 1, 2, 3, or 4 clocks. Reserved states should
not be used as unknown operation or incompatibility with future
versions may result.
EMR3 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the requirement
that AL ≤ tRCD (MIN). A typical application using this feature would
set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is
held for the time of theAL before it is issued internally to the DDR2
SDRAM device. RL is controlled by the sum of AL and CL; RL =
AL+CL. Write latency (WL) is equal to RL minus one clock; WL =
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2 SDRAM
available commands, including CKE power-down modes, and
bank-to-bank commands.
AL + CL - 1 x tCK
.
EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions beyond
those controlled by the mode register. Currently all bits in EMR2
are reserved, as shown in Figure 8. The EMR2 is programmed
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
1
2
BA2
BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
Extended mode
register (Ex)
16 15 14
MRS
n
12 11 10
9
8
7
6
5
4
3
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E15 E14
Mode Register Set
Mode register (MR)
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Notes:
1. E16 (BA2) is only applicable for densities ≥1Gb, is reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved for future use and must be programmed to “0.”
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev.1
13
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