W3H32M64EA-XSBX
ADVANCED
left floating. This function is also used to enable/disable RDQS#. If
RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then
both DQS# and RDQS# will be enabled.
DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit E0
during the LM command, as shown in Figure 7. The DLL must
be enabled for normal operation. DLL enable is required during
power-up initialization and upon returning to normal operation after
having disabled the DLLfor the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL
using an LM command.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by bit E12, as shown in
Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,
RDQS, RDQS#) function normally. When disabled (E12 = 1), all
DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are
disabled, thus removing output buffer current. The output disable
feature is intended to be used during ICC characterization of read
current.
The DLL is automatically disabled when entering SELF REFRESH
operation and is automatically re-enabled and reset upon exit of
SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a READ command can be issued, to
allow time for the internal clock to synchronize with the external
clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6
of the EMR, as shown in Figure 7. The ODT feature is designed
to improve signal integrity of the memory channel by allowing the
DDR2 SDRAM controller to independently turn on/off ODT for
any or all devices. RTT effective resistance values of 50Ω ,75Ω,
and 150Ω are selectable and apply to each DQ, DQS/DQS#,
RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/
LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective
resistance value is elected by enabling switch “sw1,” which enables
all R1 values that are 150Ω each, enabling an effective resistance
of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2
values that are 300Ω each, enable an effective ODT resistance
of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of
100Ω enabling effective resistance of 50Ω Reserved states should
not be used, as unknown operation or incompatibility with future
versions may result.
OUTPUT DRIVE STRENGTH
The output drive strength is defined by bit E1, as shown in Figure
7. The normal drive strength for all outputs are specified to be
SSTL_18. Programming bit E1 = 0 selects normal (full strength)
drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 60 percent of
the SSTL_18 drive strength. This option is intended for the support
of lighter load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is
the complement of the differential data strobe pair DQS/DQS#.
When disabled (E10 = 1), DQS is used in a single ended mode
and the DQS# ball is disabled. When disabled, DQS# should be
The ODT control ball is used to determine when RTT(EFF) is turned
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
1
2
BA2
BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
Extended mode
register (Ex)
16 15 14
n
0
12 11 10
9
0
8
0
7
6
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
SRT 0
MRS
0
E15 E14
Mode Register Set
Mode register (MR)
E7
0
SRT Enable
0
0
1
1
0
1
0
1
1X refresh rate (0°C to 85°C)
2X refresh rate (>85°C)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
1
Notes:
1. E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be programmed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved for future use and must be programmed to “0.”
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev.1
12
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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