欢迎访问ic37.com |
会员登录 免费注册
发布采购

W3H32M64EA-400SBM 参数 Datasheet PDF下载

W3H32M64EA-400SBM图片预览
型号: W3H32M64EA-400SBM
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX64, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 27 页 / 1197 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
 浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第10页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第11页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第12页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第13页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第15页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第16页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第17页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第18页  
W3H32M64EA-XSBX  
ADVANCED  
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS  
Notes: 1–3 apply to the entire table  
CKE  
BA2  
BA0  
An  
A11  
Function  
CS#  
RAS#  
CAS#  
WE#  
A10  
A9-A0  
Notes  
Previous  
Cycle  
Current  
Cycle  
LOAD MODE  
REFRESH  
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA  
X
OP Code  
4, 6  
X
X
X
X
X
X
SELF-REFRESH Entry  
L
X
X
H
H
H
H
SELF-REFRESH Exit  
L
H
X
X
X
X
4, 7  
6
Single bank precharge  
All banks PRECHARGE  
Bank activate  
H
H
H
H
H
H
BA  
X
X
X
L
H
X
X
L
H
BA  
Row Address  
4
Column  
Address  
Column  
Address  
WRITE  
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
BA  
BA  
BA  
BA  
L
H
L
4, 5, 6, 8  
Column  
Address  
Column  
Address  
WRITE with auto precharge  
READ  
4, 5, 6, 8  
4, 5, 6, 8  
4, 5, 6, 8  
Column  
Address  
Column  
Address  
H
H
Column  
Address  
Column  
Address  
READ with auto precharge  
H
NO OPERATION  
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT  
POWER-DOWN entry  
H
L
L
X
X
X
X
X
X
X
X
9
9
H
L
POWER-DOWN exit  
H
Notes:  
1. All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.  
2. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.  
3. “X” means “H or L” (but a dened logic level) for valid IDD measurements.  
4. BA2 is only applicable for densities 1Gb.  
5. An n is the most signicant address bit for a given density and conguration. Some larger address bits may be “Don’t Care” during column addressing, depending on density and conguration.  
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD MODE command selects which mode register is programmed.  
7. SELF REFRESH exit is asynchronous.  
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted.  
9. The power-down mode does not perform any REFRESH operations. The duration of powerdown is limited by the refresh requirements outlined in the AC parametric section.  
Microsemi Corporation reserves the right to change products or specications without notice.  
August 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev.1  
14  
Microsemi Corporation • (602) 437-1520 • www.microsemi.com  
 复制成功!