W3H32M64EA-XSBX
ADVANCED
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation
of the DDR2 SDRAM. This definition includes the selection of a
burst length, burst type, CL, operating mode, DLL RESET, write
recovery, and power-down mode, as shown in Figure 5. Contents of
the mode register can be altered by re-executing the LOAD MODE
(LM) command. If the user chooses to modify only a subset of the
MR variables, all variables (M0–M14) must be programmed when
the command is issued.
1
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14
n
12 11 10
PD WR
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
0
MR
0
DLL TM CAS# Latency BT Burst Length
M2 M1 M0 Burst Length
M12 PD Mode
Mode
Normal
Test
M7
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
4
0
Fast exit
(normal)
1
The mode register is programmed via the LM command (bits
BA1–BA0 = 0, 0) and other bits (M12–M0) will retain the stored
information until it is programmed again or the device loses power
(except for bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the memory array,
provided it is performed correctly.
1
Slow exit
(low power)
8
DLL Reset
No
M8
0
Reserved
Reserved
Reserved
Reserved
1
Yes
Write Recovery
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
Burst Type
Sequential
Interleaved
M3
0
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specified time tMRD before
initiating any subsequent operations such as anACTIVE command.
Violating either of these requirements will result in unspecified
operation.
1
CAS Latency (CL)
M6 M5 M4
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
M15 M14
Mode Register Definition
3
4
5
6
7
0
0
1
1
0
1
0
1
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
BURST LENGTH
Burst length is defined by bits M0–M3, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length dete rmines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Notes:
1. M16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and
must be programmed to “0.”
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12)
are reserved for future use and must be programmed to “0.”
3. Not all listed WR and CL options are supported in any individual speed grade.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleave address ordering is supported; however, sequential
address ordering is nibble-based.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev.1
8
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