W3H128M72E-XSBX / W3H128M72E-XNBX
Document Title
1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History Continued
Rev #
History
Release Date Status
Rev 11
Changes (Pg. 1-3, 5-27)
September 2012
Final
11.1 Remove ±0.1V from Core Supply Voltage and I/O Supply Voltage
11.2 Remove numbers from CAS latency
11.3 Change note in Figure 2
11.4 Change note in Figure 3
11.5 Correct typos in Description
11.6 Update diagram in Figure 4
11.7 Update notes 3-16 for Figure 4
11.8 Correct typos on page 7; update diagram in Figure 5
11.9 Correct typos on page 8
11.10 Correct typos on page 9
11.11 Correct typos and update diagram in Figure 7 on page 10
11.12 Correct typos on page 11
11.13 Correct typos update diagram in Figure 8 on page 12
11.14 Correct typos update diagram in Figure 9 on page 13
11.15 Update Table 3 – Truth Table - DDR2 Commands
11.16 Correct typos on page 15, 16, and 17
11.17 Correct typo in Table 4
11.18 Correct typos on page 19
11.19 Update Absolute Maximum Ratings, DC Operating Conditions and
Input/Output Capacitance charts on page 20
11.20 Update BGA Thermal Resistance chart on page 21
11.21 Update DDR2 ICC Specifications and Conditions chart on page 22
11.22 Delete subtitle from AC Timing Parameters chart on pages 23, 24 and
25; update Refresh values same chart
11.23 Update BGA Thermal Resistance chart on page 21
11.24 Add note to Figures 14 and 15
Rev 12
Changes (Pg. All)
July 2016
Final
12.1 Change document layout from Microsemi to Mercury Systems
Mercury Systems reserves the right to change products or specifications without notice.
© 2016 Mercury Systems. All rights reserved.
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