MX25L1635D
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
- VCC minimum at power-up stage and then after a delay of tVSL
-GNDatpower-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
Aninternalpower-onreset(POR)circuitmayprotectthedevicefromdatacorruptionandinadvertentdatachangeduring
powerupstate.WhenVCCislowerthanVWI(PORthresholdvoltagevalue),theinternallogicisresetandtheflashdevice
has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device
is fully accessible for commands like write enable(WREN), page program (PP), quad page program (4PP), continuously
program(CP),sectorerase(SE),blockerase(BE),chiperase(CE),WRSCURandwritestatusregister(WRSR).IftheVCC
doesnotreachtheVCCminimumlevel,thecorrectoperationisnotguaranteed.Thewrite,erase,andprogramcommand
should be sent after the below time delay:
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW
has not passed.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generallyaround0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any
command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
P/N:PM1374
REV. 1.5, OCT. 01, 2008
25
Macronix [ MACRONIX INTERNATIONAL ]
