MX25L1635D
Table 8. Security Register Definition
bit7
x
bit6
x
bit5
x
bit4
bit3
x
bit2
x
bit1
LDSO
bit0
Continuously
Program mode
(CP mode)
(indicate if Secrured OTP
lock-down
0 = not lock-
down
1 = lock-down
(cannot
indicator bit
0=normal
Program mode
1=CP mode
(default=0)
0 = non-
factory lock
reserved
reserved
reserved
reserved
reserved
program/erase 1 = factory
OTP) lock
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit non-volatile bit non-volatile bit
(22)WriteSecurityRegister(WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instructionisnotrequiredbeforesendingWRSCURinstruction. TheWRSCURinstructionmaychangethevaluesofbit1
(LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP
area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N:PM1374
REV. 1.5, OCT. 01, 2008
24
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