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MX25L1635DMI-12G 参数 Datasheet PDF下载

MX25L1635DMI-12G图片预览
型号: MX25L1635DMI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存 [16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 50 页 / 728 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L1635D  
DEVICE OPERATION  
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.  
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until  
next CS# falling edge. In standby mode, all SO pins of this LSI should be High-Z.  
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next  
CS# rising edge.  
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The  
difference of Serial mode 0 and mode 3 is shown as Figure 2.  
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS, REMS2  
and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted  
out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, 4PP, CP, RDP, DP,  
ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be  
rejected and not executed.  
6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand  
not affect the current operation of Write Status Register, Program, Erase.  
Figure 1. Serial Modes Supported  
CPOL CPHA  
shift in  
shift out  
SCLK  
SCLK  
(Serial mode 0)  
(Serial mode 3)  
0
1
0
1
SI  
MSB  
SO  
MSB  
Note:  
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not  
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is  
supported.  
P/N:PM1374  
REV. 1.5, OCT. 01, 2008  
13