MX25L12835F
9-17. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” and SPI “EBh” commands support enhance mode. The performance enhance mode is not sup-
ported in dual I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh
can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.
Issuing ”FFh” command can also exit enhance mode. The system then will leave performance enhance mode and
return to normal operation.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low sending 4
→
READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit
→
→
P[7:0] 4 dummy cycles (Default) data out still CS# goes high
CS# goes low (reduce 4 Read instruction)
→
→
→
→
3-bytes random access address.
P/N: PM1795
REV. 1.0, OCT. 23, 2012
46
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