MX25L12835F
9-14. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next high-
er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low
sending QREAD instruction → 3-byte address on
→
SI
8 dummy cycle (Default)
data out interleave on SO3, SO2, SO1 & SO0
to end QREAD operation can
→
→
→
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 30. Quad Read Mode Sequence
CS#
29 30 31 32 33
38 39 40 41 42
0
1
2
3
4
5
6
7
8
9
SCLK
…
…
Configurable
dummy cycles
Data
Out 1
Data Data
Out 2 Out 3
Command
6B
24 ADD Cycles
…
A23A22
A2 A1 A0
D4 D0 D4 D0 D4
SIO0
SIO1
SIO2
SIO3
High Impedance
High Impedance
High Impedance
D5 D1 D5 D1 D5
D6 D2 D6 D2 D6
D7 D3 D7 D3 D7
P/N: PM1795
REV. 1.0, OCT. 23, 2012
42
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