MX25L12835F
9-18. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be is-
sued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 37. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFh
SIO0
SIO1
SIO2
Don’t Care
Don’t Care
Don’t Care
SIO3
Figure 38. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFFFFFFFh
SIO[3:0]
P/N: PM1795
REV. 1.0, OCT. 23, 2012
49
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