MX25L12835F
9-15. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg-
ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ.
The first address byte can be at any location. The address is automatically increased to the next higher address af-
ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending
→
4READ instruction 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out
→
→
→
interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out.
→
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence
of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 3-byte address interleave
→
→
on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out interleave on SIO3, SIO2, SIO1 & SIO0 to
→
→
→
end 4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1795
REV. 1.0, OCT. 23, 2012
43
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