MX25L12835F
Figure 36. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
EBh
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data In
Data Out
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
CS#
SCLK
n+1 .............
Mode 0
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data Out
6 Address cycles
(Note)
performance
enhance
indicator
Configurable
Dummy Cycle (Note 1)
Notes:
1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
configuration register.
P/N: PM1795
REV. 1.0, OCT. 23, 2012
48
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