MX25L12835F
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in
SPI mode.
Figure 6. Write Enable (WREN) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
06h
SI
High-Z
SO
Figure 7. Write Enable (WREN) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Mode 0
Command
SIO[3:0]
06h
P/N: PM1795
REV. 1.0, OCT. 23, 2012
20
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