Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
Don’t put high-value ceramic capacitors directly across
ensure that the conduction losses at minimum input volt-
age don’t exceed the package thermal limits or violate
the overall thermal budget. Check to ensure that con-
duction losses plus switching losses at the maximum
input voltage don’t exceed the package ratings or violate
the overall thermal budget.
the fast feedback inputs (FB to GND) without taking pre-
cautions to ensure stability. Large ceramic capacitors
can have a high ESR zero frequency and cause erratic,
unstable operation. However, it’s easy to add enough
series resistance simply by placing the capacitors a cou-
ple of inches downstream from the junction of the induc-
tor a nd FB p in (s e e the All-Ce ra mic -Ca p a c itor
Application section).
Choose a low-side MOSFET (Q2) that has the lowest
possible R , comes in a moderate to small pack-
DS(ON)
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1710/MAX1711 DL gate driver can drive Q2; in
other words, check that the gate isn’t pulled up by the
high-side switch turning on due to parasitic drain-to-gate
c a p a c ita nc e , c a us ing c ros s -c ond uc tion p rob le ms .
Switching losses aren’t an issue for the low-side MOS-
FET, since it’s a zero-voltage switched device when
used in the buck topology.
Unstable operation manifests itself in two related but dis-
tinctly different ways: double-pulsing and fast-feedback
loop instability.
Double-pulsing occurs due to noise on FB or because
the ESR is so low that there isn’t enough voltage ramp in
the output voltage (FB) signal. This “fools” the error com-
parator into triggering a new cycle immediately after the
400ns minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
MOS FET P o w e r Dis s ip a t io n
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
2
PD(Q1) = (V
/ V
) · I
· R
DS(ON)
OUT
BATT(MIN)
LOAD
Generally, a small high-side MOSFET is desired in order
to re d uc e s witc hing los s e s a t hig h inp ut volta g e s .
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (see MAX1710
Evaluation Kit manual) and carefully observe the output
voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Don’t allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
However, the R
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the switch-
ing (AC) losses equal the conduction (R
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
required to stay within package
DS(ON)
) losses.
DS(ON)
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2F switching loss equation. If the high-side MOSFET
In p u t Ca p a c it o r S e le c t io n
The inp ut c a p a c itor mus t me e t the rip p le c urre nt
you’ve chosen for adequate R
at low battery volt-
DS(ON)
requirement (I
) imposed by the switching currents.
RMS
ages becomes extraordinarily hot when subjected to
, you must reconsider your choice of MOS-
Non-tantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power-up
surge currents.
V
BATT(MAX)
FET.
Calculating the power dissipation in Q1 due to switching
losses is difficult, since it must allow for difficult to quanti-
fy factors that influence the turn-on and turn-off times.
These factors include the internal gate resistance, gate
charge, threshold voltage, source inductance, and PC
board layout characteristics. The following switching loss
calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including
a sanity check using a thermocouple mounted on Q1.
V
(V
− V
)
OUT BATT
V
OUT
I
=I
LOAD
RMS
BATT
P o w e r MOS FET S e le c t io n
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
______________________________________________________________________________________ 19
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
