Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
+5V
V
IN
= 7V TO 24V*
0.1µF
20Ω
C1
1µF
V
DD
V+
V
CC
5Ω
ON/OFF
SHDN
SKIP
BST
DH
Q1
Q2
0.5µH
R1
R2
1.6V AT 7A
CPU
0.1µF
MAX1711
LX
D0
D1
D2
D3
D4
C2
DAC
INPUTS
DL
PGND
GND
FB
0.22µF
1k
REF
CC
1k
1k
0/MAX71
FBS
470pF
GNDS
TON
C1 = 4 x 4.7µF/25V TAIYO YUDEN (TMK325BJ475K)
C2 = 6 x 47µF/10V TAIYO YUDEN (LMK550BJ476KM)
1nF
R1 + R2 = 5mΩ MINIMUM OF PCB TRACE RESISTANCE (TOTAL)
* FOR HIGHER MINIMUM INPUT VOLTAGE,
* LESS OUTPUT CAPACITANCE IS REQUIRED.
Figure 7. All-Ceramic-Capacitor Application
current limit and cause the fault latch to trip. To protect
against this possibility, you must “overdesign” the circuit
Table 5. Approximate K-Factors Errors
TON
K
APPROXIMATE
K-FACTOR
MIN V
BATT
to tolerate I
= I
+ (LIR / 2) · I
,
LOAD
LIMIT(HIGH)
LOAD(MAX)
SETTING FACTOR
AT V
= 2V
OUT
where I
is the maximum valley current allowed
LIMIT(HIGH)
(kHz)
200
(µs-V)
5
ERROR (%)
(V)
2.6
2.9
3.2
3.6
by the current-limit circuit, including threshold tolerance
a nd on-re s is ta nc e va ria tion. This me a ns tha t the
MOSFETs must be very well heatsinked. If short-circuit
protection without overload protection is enough, a nor-
±10
±10
300
3.3
2.5
1.8
400
±12.5
±12.5
mal I
value can be used for calculating component
LOAD
stresses.
550
Choose a Schottky diode D1 having a forward voltage
low enough to prevent the Q2 MOSFET body diode from
turning on during the dead time. As a general rule, a
diode having a DC current rating equal to 1/3 of the load
current is sufficient. This diode is optional, and if efficien-
cy isn’t critical it can be removed.
2
C
V
f I
LOAD
RSS BATT(MAX)
PD(switching) =
I
GATE
where C
and I
is the reverse transfer capacitance of Q1
is the peak gate-drive source/sink current (1A
RSS
GATE
Ap p lic a t io n Is s u e s
typical).
Dro p o u t P e rfo rm a n c e
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the non-adjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slowest (200kHz) on-time setting.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off-times. Manufacturing tolerances and internal
For the low-side MOSFET, Q2, the worst-case power dis-
sipation always occurs at maximum battery voltage:
2
· R
LOAD DS(ON)
PD(Q2) = (1 - V
/ V
) · I
OUT
BATT(MAX)
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
but are not quite high enough to exceed the
LOAD(MAX)
20 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
