Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
direct traces making a Kelvin sense connection to the
source and drain terminals.
and forces the DL gate driver high (in order to enforce
output overvoltage protection) until V rises above
CC
4.2V, whereupon an internal digital soft-start timer begins
to ramp up the maximum allowed current limit. The ramp
occurs in five steps: 20%, 40%, 60%, 80%, and 100%,
with 100% current available after 1.7ms ±50%.
MOS FET Ga t e Drive rs (DH, DL)
The DH and DL drivers are optimized for driving moder-
ate-size, high-side and larger, low-side power MOSFETs.
This is consistent with the low duty factor seen in the
A continuously adjustable, analog soft-start function can
notebook CPU environment, where a large V
- V
BATT
OUT
be realized by adding a capacitor in parallel with R
at
LIM
differential exists. An adaptive dead-time circuit monitors
the DL output and prevents the high-side FET from turn-
ing on until DL is fully off. There must be a low-resis-
tance, low-inductance path from the DL driver to the
MOSFET gate in order for the adaptive dead-time circuit
to work properly. Otherwise, the sense circuitry in the
MAX1710/MAX1711 will interpret the MOSFET gate as
“off” while there is actually still charge left on the gate.
Use very short, wide traces measuring 10 to 20 squares
(50 to 100 mils wide if the MOSFET is 1 inch from the
MAX1710/MAX1711).
ILIM. This soft-start method requires a minimum interval
between power-down and power-up to allow R
charge the capacitor.
to dis-
LIM
P o w e r-Go o d Ou t p u t (P GOOD)
The output (FB) is continuously monitored for undervolt-
age by the PGOOD comparator, except in shutdown or
standby mode. The -5% undervoltage trip threshold is
measured with respect to the nominal unloaded output
voltage, as set by the DAC. If the DAC code increases in
steps greater than 1LSB, it is likely that PGOOD will
momentarily go low. In shutdown and standby modes,
PGOOD is actively held low. The PGOOD output is a true
open-drain type with no parasitic ESD diodes. Note that
the PGOOD undervoltage detector is completely inde-
pendent of the output UVP fault detector.
The dead time at the other edge (DH turning off) is deter-
mined by a fixed 35ns (typical) internal delay.
The internal pull-down transistor that drives DL low is
robust, with a 0.5Ω typical on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the massive low-side synchronous-
rectifier MOSFET. However, you might still encounter
some combinations of high- and low-side FETs that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI-producing shoot-through currents.
This can often be remedied by adding a resistor in series
with BST, which increases the turn-on time of the high-
side FET without degrading the turn-off time.
Ou t p u t Ove rvo lt a g e P ro t e c t io n (OVP )
The overvoltage protection circuit is designed to protect
against a shorted high-side MOSFET by drawing high
current and blowing the battery fuse. The FB node is
continuously monitored for overvoltage. The overvoltage
trip threshold tracks the DAC code setting. If the output
is more than 12.5% above the nominal regulation point
for the MAX1710 (2.25V absolute for the MAX1711),
overvoltage protection (OVP) is triggered and the circuit
shuts down. The DL low-side gate-driver output is then
DAC Co n ve rt e r (D0 –D4 )
The digital-to-analog converter (DAC) programs the out-
put voltage. It receives a digital code from pins on the
CPU module that are either hard-wired to GND or left
open-circuit. Note that the codes don’t match any desk-
top VRM codes. The MAX1710/MAX1711 contain weak
internal pull-ups on each input in order to eliminate exter-
nal resistors.
latched high until SHDN is toggled or V
power is
CC
cycled below 1V. This action turns on the synchronous-
rectifier MOSFET with 100% duty and, in turn, rapidly dis-
charges the output filter capacitor and forces the output
to ground.
If the condition that caused the overvoltage (such as a
shorted high-side MOSFET) persists, the battery fuse will
blow. Note that DL going high can have the effect of
causing output polarity reversal, due to energy stored in
the output LC at the instant OVP activates. If the load
can’t tolerate being forced to a negative voltage, it may
be desirable to place a power Schottky diode across the
output to act as a reverse-polarity clamp (Figure 1). The
MAX1710/MAX1711 itself can be affected by the FB pin
going below ground, with the negative voltage coupling
into SHDN. It may be necessary to add 1kΩ resistors in
series with FB and FBS (Figure 7).
When changing MAX1710 DAC codes while powered
up, the over/undervoltage protection features can be
activated if the code is changed more than 1LSB at a
time. For applications needing the capability of changing
DAC codes “on-the-fly,” use the MAX1711.
P OR, UVLO, a n d S o ft -S t a rt
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and soft-start
counter, and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switching
______________________________________________________________________________________ 15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
