Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
tor. In some cases, there may be no room for electrolyt-
V
BATT
ics, creating a need for a DC-DC design that uses noth-
ing but ceramics.
DH
The all-ceramic-capacitor application of Figure 7 has the
same basic performance as the 7A Standard Application
Circuit, but replaces the tantalum output capacitors with
ceramics. This design relies on having a minimum of
5mΩ parasitic PC board trace resistance in series with
the capacitor in order to reduce the ESR zero frequency.
This small amount of resistance is easily obtained by
locating the MAX1710/MAX1711 circuit two or three inch-
es away from the CPU, and placing all the ceramic
capacitors close to the CPU. Resistance values higher
tha n 5mΩ jus t imp rove the s ta b ility (whic h c a n b e
observed by examining the load-transient response
c ha ra c te ris tic a s s hown in the Typ ic a l Op e ra ting
Characteristics). Avoid adding excess PC board trace
resistance, as there’s an efficiency penalty. 5mΩ is suffi-
cient for the 7A circuit.
V
OUT
MAX1710
DL
R1
R2
FB
FBS
1k
GNDS
Figure 8. Setting V
with a Resistor-Divider
OUT
Outp ut ove rs hoot d e te rmine s the minimum outp ut
capacitance requirement. In this example, the switching
frequency has been increased to 550kHz and the induc-
tor value has been reduced to 0.5µH (compared to
300kHz and 2µH for the standard 7A circuit) in order to
minimize the energy transferred from inductor to capaci-
tor during load-step recovery. Even so, the amount of
overshoot is high enough (80mV) that for the MAX1710,
it’s wise to disable OVP or use the MAX1711 with its fixed
2.25V overvoltage protection threshold to avoid tripping
the fault latch (see the overshoot equation in the Output
Capacitor Selection section). The efficiency penalty for
operating at 550kHz is about 2% to 3%, depending on
the input voltage.
propagation delays introduce an error to the TON K-fac-
tor. This error is higher at higher frequencies (Table 5).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
V
SAG
equation in the Design Procedure).
Dropout Design Example: V
= 3V min, V
=
OUT
BATT
2V, f = 300kHz. The required duty is (V
+ V ) /
OUT
SW
(V
BATT
- V ) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The
SW
worst-case on-time is (V
+ 0.075) / V
· K =
OUT
BATT
2.075V / 3V · 3.35µs-V · 90% = 2.08µs. The IC duty-fac-
tor limitation is:
t
ON(MIN)
Two optional 1kΩ resistors are placed in series with FB
and FBS. These resistors prevent the negative output
volta g e s p ike (tha t re s ults from trip p ing OVP) from
pulling SHDN low via its internal ESD diode, which tends
to clear the fault latch, causing “hiccup” restarts.
DUTY =
= 2.08µs + 500ns = 80.6%
t
+ t
ON(MIN) OFF(MAX)
which meets the required duty.
Remember to include inductor resistance and MOSFET
S e t t in g V
w it h a Re s is t o r-Divid e r
OUT
on-state voltage drops (V ) when doing worst-case
SW
The output voltage can be adjusted with a resistor-
divider rather than the DAC if desired (Figure 8). The
drawback of this practice is that the on-time doesn’t
automatically receive correct compensation for changing
output voltage levels. This can result in variable switch-
ing frequency as the resistor ratio is changed and/or
excessive switching frequency. The equation for adjust-
ing the output voltage is:
dropout duty-factor calculations.
All-Ce ra m ic -Ca p a c it o r Ap p lic a t io n
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR, are non-combustible,
are relatively small, and are nonpolarized. On the other
hand, they’re expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies (affecting stability). In addition, they
can cause output overshoot when going abruptly from
full-load to no-load conditions, unless there are some
bulk tantalum or electrolytic capacitors in parallel to
absorb the stored energy in the induc-
R1
V
= V −1% 1+
FB
(
)
OUT
R2
______________________________________________________________________________________ 21
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
