Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
is cheap and can work well at 200kHz. The core must be
Vp -p
large enough not to saturate at the peak inductor current
(I ).
R
≤
ESR
PEAK
LIR I
LOAD(MAX)
I
= I
+ (LIR / 2) · I
PEAK
LOAD(MAX) LOAD(MAX)
The actual microfarad capacitance value required relates
to the physical size needed to achieve low ESR, as well
as to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums,
OS-CONs, and other electrolytics).
S e t t in g t h e Cu rre n t Lim it
The minimum c urre nt-limit thre s hold mus t b e g re a t
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley
of the inductor current occurs at I
of the ripple current, therefore:
minus half
LOAD(MAX)
When using low-capacity filter capacitors such as ceram-
ic or polymer types, capacitor size is usually determined
by the capacity needed to prevent the overvoltage pro-
tection circuit from being tripped when transitioning from
a full-load to a no-load condition. The capacitor must be
large enough to prevent the inductor’s stored energy from
launching the output above the overvoltage protection
threshold. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the ris-
I
> I
- (LIR / 2) · I
LOAD(MAX) LOAD(MAX)
LIMIT(LOW)
where I
= minimum current-limit threshold volt-
LIMIT(LOW)
age divided by the R
minimum current-limit threshold (100mV default setting)
is 90mV. Use the worst-case maximum value for R
from the MOSFET Q2 data sheet, and add some margin
for the rise in R with temperature. A good general
rule is to allow 0.5% additional resistance for each °C of
temperature rise.
of Q2. For the MAX1710, the
DS(ON)
DS(ON)
0/MAX71
DS(ON)
ing load edge is no longer a problem (see also V
SAG
equation under Design Procedure).
With integrators disabled, the amount of overshoot due to
stored inductor energy can be calculated as:
Examining the 7A notebook CPU circuit example with a
maximum R
= 15mΩ at high temperature reveals
DS(ON)
the following:
2
2
C
V
+L I
OUT OUT PEAK
∆V =
− V
OUT
I
= 90mV / 15mΩ = 6A
LIMIT(LOW)
C
OUT
6A is greater than the valley current of 5.25A, so the cir-
cuit can easily deliver the full rated 7A using the default
100mV nominal ILIM threshold.
where I
is the peak inductor current. To absolutely
PEAK
minimize the overshoot, disable the integrator first, since
the inherent delay of the integrator can cause extra “run-
on” switching cycles to occur after the load change.
When adjusting the current limit, use a 1% tolerance R
resistor to prevent a significant increase of errors in the
current-limit tolerance.
LIM
Ou t p u t Ca p a c it o r S t a b ilit y Co n s id e ra t io n s
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The point of instability is
given by the following equation:
Output Ca pa c itor Se le c tion
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to sat-
isfy stability requirements. Also, the capacitance value
must be high enough to absorb the inductor energy
going from a full-load to no-load condition without tripping
the overvoltage protection circuit.
f
f
=
ESR
π
1
where f
=
ESR
2 π R
C
F
ESR
In CPU V
converters and other applications where
CORE
the output is subject to violent load transients, the output
capacitor’s size depends on how much ESR is needed to
prevent the output from dipping too low under a load
transient. Ignoring the sag due to finite capacitance:
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequencies
of 15kHz. In the design example used for inductor selec-
tion, the ESR needed to support 50mVp-p ripple is
50mV/3.5A = 14.2mΩ. Three 470µF/4V Kemet T510 low-
ESR tantalum capacitors in parallel provide 15mΩ max
ESR. Their typical combined ESR results in a zero at
14.1kHz, well within the bounds of stability.
V
DIP
LOAD(MAX)
R
≤
ESR
I
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
18 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
