Hig h -S p e e d , Dig it a lly Ad ju s t e d
S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
Dyn a m ic DAC Co d e Ch a n g e s
(MAX1 7 1 1 )
Hig h -P o w e r, Dyn a m ic a lly
Ad ju s t a b le CP U Ap p lic a t io n
Changing the output voltage dynamically by switching
DAC c od e s “on-the -fly” c a n b e us e d to he lp ma ke
power-savings/performance trade-offs in the host sys-
tem. Several important design issues arise from this
practice.
The MAX1711 V
regulator of Figure 10 is designed
CORE
to have its output voltage switched between 1.3V and
1.45V in less than 100µs, while causing a minimum level
of input surge current. To this end, the output capacitors
were selected for having the correct value to a) support
the needed ESR, b) prevent excess load-recovery over-
shoot, and c) minimize input surge currents.
First, know that attempting to slew the output upward
quickly causes large current surges at the battery as the
IC goes into output current limiting during the transition.
Surge currents can be controlled either by counting the
DAC code slowly (50kHz or slower rate suggested), or
The optional 74HC86 exclusive-OR gate detects code
transitions on each of the four most-significant DAC
inputs. The transition detector output goes to a precision
pulse stretcher, a timer which extends the pulse for 75µs
(nominal). This signal then feeds three circuits: the
power-good detector, the SKIP input, and the ILIM cur-
rent-limit control input, thus reducing the current-limit
threshold during the transition interval (in order to reduce
b a tte ry c urre nt s urg e s ). Like wis e , SKIP g oing hig h
asserts forced PWM mode in order to drag the output
voltage down to the new value. Forced PWM mode is
incompatible with good light-load efficiency due to
inductor-current recirculation losses and gate-drive loss-
es. Therefore, SKIP is driven high only during the 100µs
max transition interval.
by modulating the I
current-limit threshold.
LIM
The DAC inputs must be driven quickly to the new value
so the device doesn’t wrongly interpret a disallowed
DAC code from the transitory value. Use 100ns maxi-
mum rise and fall times.
Selecting the output capacitors in dynamically adjusted
V
CORE
applications can be tricky due to trade-offs
between capacitor capacity and ESR. In other words, if
the capacitor has sufficiently low ESR to meet the load-
transient response specification, its large capacity may
cause excessive input surge currents. On the other
hand, a purely ceramic capacitor may not have enough
capacity to prevent overvoltage during the transition from
full- to no-load condition (see the overshoot equation
under Output Capacitor Selection). It may be necessary
to mix capacitor types or use specialized capacitors
such as those shown in Figure 7 in order to achieve the
required ESR while staying within the min/max capaci-
tance value window.
The power-good output signal is the logical OR of the
75µs timer signal and the MAX1711 PGOOD signal. The
internal PGOOD detector circuit monitors only output
und e rvolta g e ; PGOOD will p rob a b ly g o low d uring
upward transitions, but not downward. The final power-
good output will always go low for at least 75µs due to
the timer signal.
Load current capability is 15A peak and 12A continuous
ove r a 10V to 22V inp ut ra ng e . All thre e MOSFETs
require good heatsinking. See the MAX1711 EV Kit
Manual for a complete bill of materials.
If the minimum load is very light, it may be necessary to
assert forced PWM mode (via SKIP) during the transition
period to guarantee some output sink current capability.
Otherwise, the output voltage won’t ramp downwards
until pulled down by external load current.
P C Bo a rd La yo u t Gu id e lin e s
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The switch-
ing power stage requires particular attention (Figure 11).
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
Using forced PWM mode repeatedly to ensure sink cur-
rent capability can have side effects, however. The ener-
gy taken from the output by the synchronous rectifier
isn’t lost, but is instead returned to the input. If the fre-
quency of the high-to-low output voltage transition is high
enough, efficiency will be degraded by the resistive “fric-
tion” losses associated with shuttling energy between
input and output capacitors. Also, if the output is being
overdriven by an external source (such as an external
docking-station power supply), forced PWM mode may
cause the battery voltage to become pumped up, possi-
bly overvoltaging the battery.
•
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
•
Tie GND and PGND together close to the IC. Carefully
follow the grounding instructions under step 4 of the
Layout Procedure.
______________________________________________________________________________________ 23
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
