MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
CNVST
CS
t
CSW
EOC
t
CNV_INT
1
16
1
16
SCLK
DIN
SET MODE REG
SET MODE REG
DOUT
INTERNAL
OSCILLATOR ON
READ DATA FROM FIFO
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 6. Internal Conversions with CNVST
UP TO N INTERNALLY
CLOCKED ACQUISITIONS
AND CONVERSIONS
t
CNV_INT
(N = 1)
CS
EOC
1
17
1
16
SCLK
SET MODE REG
SWCNV = 1
SET MODE REG
DIN
DOUT
MODE CONTROL
INTERNAL OSCILLATOR ON
READ DATA FROM FIFO
SCAN OPERATION AND
RESULTS STORED IN FIFO
Figure 7. Internal Conversions with SWCNV
���������������������������������������������������������������� Maxim Integrated Products 18