8- and 4-Channel, 3 ꢀ ꢁREF
Multirange Inputs, Serial 14-Bit ADCs
2/MAX103
CS
SSTRB
SCLK
BYTE 1
BYTE 2
BYTE 3
***
DIN
S
C2 C1 C0
0
0
0
0
HIGH
IMPEDANCE
DOUT
B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
f
≈ f
SAMPLE SCLK
/ 24 + f / 28
INTCLK
SAMPLING INSTANT
t
ACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
100ns to 400ns
INTCLK**
f
≈ 4.5MHz
INTCLK
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
***DIN BYTES 2 TO 4 MUST BE DRIVEN TO LOGIC 0 TO OBTAIN A VALID CONVERSION.
Figure 4. Internal Clock-Mode Conversion (Mode 2)
R2
MAX1032
MAX1033
R1
1.0
ALL MODES
*R
SOURCE
IN_+
0.6
0.2
ANALOG
SIGNAL
SOURCE
V
SJ
R2
-0.2
-0.6
-1.0
*R
R1
V
SOURCE
IN_+
ANALOG
SIGNAL
SOURCE
-3 x V
2
+3 x V
2
REF
REF
SJ
-3 x V
0
+3 x V
REF
REF
ANALOG INPUT VOLTAGE (V)
*MINIMIZE R
TO AVOID GAIN ERROR AND DISTORTION.
SOURCE
Figure 5. Analog Input Current vs. Input Voltage
______________________________________________________________________________________ 17
Figure 6. Simplified Analog Input Circuit
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
