8- and 4-Channel, 3 ꢀ ꢁREF
Multirange Inputs, Serial 14-Bit ADCs
2/MAX103
CS
SCLK
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
DIN
S
C2 C1 C0
0
0
0
0
**
f
≈ f / 32
SAMPLE SCLK
SAMPLING INSTANT
t
ACQ
ANALOG INPUT
TRACK AND HOLD*
HOLD
TRACK
HOLD
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DOUT
B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**DIN BYTES 2 TO 4 MUST BE DRIVEN TO LOGIC 0 TO OBTAIN A VALID CONVERSION.
Figure 2. External Clock-Mode Conversion (Mode 0)
As a result, the analog input impedance is relatively
constant over input voltage as shown in Figure 5.
Analog Input Bandwidth
The MAX1032/MAX1033 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD
and -SFDR vs. Input Frequency plot in the Typical
Operating Characteristics.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel. For
example, to configure CH2 and CH3 for a 3 x V
dif-
REF
ferential conversion, set the CH2 analog configuration
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
byte for a differential conversion with the 3 x V range
REF
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
______________________________________________________________________________________ 15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
