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DS2154LNA2+ 参数 Datasheet PDF下载

DS2154LNA2+图片预览
型号: DS2154LNA2+
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100]
分类和应用: PC电信电信集成电路
文件页数/大小: 124 页 / 982 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers  
17. INTERLEAVED PCM BUS OPERATION  
In many architectures, the outputs of individual framers are combined into higher speed serial buses to  
simplify transport across the system. The DS21354/DS21554 can be configured to allow data and  
signaling buses to be multiplexed into higher speed data and signaling buses eliminating external  
hardware saving board space and cost.  
The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two  
SCTs to share a common bus. The 8.192MHz bus speed allows four SCTs to share a common bus. See  
Figure 17-1 for an example of four devices sharing a common 8.192MHz PCM bus. Each SCT that shares  
a common bus must be configured through software and requires the use of one or two device pins. The  
elastic stores of each SCT must be enabled and configured for 2.048MHz operation. See Figure 17-1 and  
Table 17-1.  
For all bus configurations, one SCT will be configured as the master device and the remaining SCTs will  
be configured as slave devices. In the 4.096MHz bus configuration there is one master and one slave. In  
the 8.192MHz bus configuration there is one master and three slaves. Refer to the IBO register  
description for more detail.  
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex)  
(MSB)  
(LSB)  
IBOEN  
INTSEL  
MSEL0  
MSEL1  
SYMBOL POSITION  
NAME AND DESCRIPTION  
IBO.6  
IBO.6  
IBO.5  
IBO.4  
Not Assigned. Should be set to 0.  
Not Assigned. Should be set to 0.  
Not Assigned. Should be set to 0.  
Not Assigned. Should be set to 0.  
Interleave Bus Operation Enable  
0 = Interleave Bus Operation disabled.  
1 = Interleave Bus Operation enabled.  
Interleave Type Select  
IBOEN  
IBO.3  
INTSEL  
IBO.2  
0 = Byte interleave.  
1 = Frame interleave.  
Master Device Bus Select Bit 0. See Table 17-1.  
Master Device Bus Select Bit 1. See Table 17-1.  
MSEL0  
MSEL1  
IBO.1  
IBO.0  
Table 17-1. IBO Master Device Select  
MSEL1  
MSEL0  
FUNCTION  
0
0
1
1
0
1
0
1
Slave device.  
Master device with 1 slave device (4.096MHz bus rate)  
Master device with 3 slave devices (8.192MHz bus rate)  
Reserved  
98 of 124  
 
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