DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
CHANNEL 23/31
LSB MSB
CHANNEL 24/32
CHANNEL 1/2
RSER1
MSB
LSB
F
RSYNC2
RMSYNC
RSYNC3
RCHCLK
RCHBLK 4
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1
LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED
TO ON1).
NOTE 2: RSYNC IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 3: RSYNC IN THE INPUT MODE (RCR1.5 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
CHANNEL 31
CHANNEL 32
CHANNEL 1
LSB MSB
MSB
LSB
RSER
RSYNC1
RMSYNC
2
RSYNC
CHANNEL 1
CHANNEL 32
CHANNEL 31
C
C
A
B
A
B
D
D
RSIG
RCHCLK
RCHBLK3
Note 4
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
