DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a one in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 16-2. Table 16-3 lists the device ID codes for the
SCT devices.
Table 16-2. ID Code Structure
MSB
LSB
Version
Device ID
16 bits
JEDEC
1
Contact Factory
4 bits
00010100001
1
Table 16-3. Device ID Codes
DEVICE
DS21354
DS21554
DS21352
DS21552
16-BIT ID
0005h
0003h
0004h
0002h
16.2. Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21354/554 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 16-4 for all the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions that provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See Table 16-3 and Table 16-4 for more information on bit usage.
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