DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
16.1. Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-
IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21354/DS21554 with their respective operational binary codes are shown in
Table 16-1.
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SAMPLE/PRELOAD
BYPASS
SELECTED REGISTER
Boundary Scan
Bypass
INSTRUCTION CODES
010
111
000
011
100
001
EXTEST
Boundary Scan
Bypass
CLAMP
HIGHZ
Bypass
Device Identification
IDCODE
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering
with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows
the device to shift data into the boundary scan register via JTDI using the Shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
HIGHZ
All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be
connected between JTDI and JTDO.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
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