DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
18. FUNCTIONAL TIMING DIAGRAMS
18.1. Receive
Figure 18-1. Receive-Side Timing
1
FRAME#
RFSYNC
RSYNC 1
RSYNC2
RLCLK 3
RLINK 4
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0).
NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 = 1).
NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE SA BITS.
NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE SA BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.
NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)
RCLK
CHANNEL 32
CHANNEL 1
CHANNEL 2
MSB
LSB Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8
RSER
RSYNC
RFSYNC
CHANNEL 32
CHANNEL 1
CHANNEL 2
C
D
A
A
B
B
RSIG
RCHCLK
RCHBLK1
RLCLK
Note 4
RLINK 2
Sa4 Sa5 Sa6 Sa7 Sa8
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 2: RLCLK IS PROGRAMMED TO MARK THE SA4 BIT IN RLINK.
NOTE 3: SHOWN ISA RNAF FRAME BOUNDARY.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
