DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK
CHANNEL 23
CHANNEL 24
CHANNEL 1
1
LSB MSB
LSB
F
MSB
TSER
TSSYNC
TCHCLK
TCHBLK2
NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK
CHANNEL 31
CHANNEL 32
CHANNEL 1
CHANNEL 1
LSB MSB
LSB MSB
TSER
TSSYNC
TSIG
CHANNEL 31
CHANNEL 32
A
B
A
B
C
C
D
D
A
TCHCLK
1
TCHBLK
NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31.
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