DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
18.2. Transmit
Figure 18-7. Transmit-Side Timing
1
2
3
4
5 6
7
8
9 10 11 12 13
1 2 3 4 5 6 7 8 9 10
14 15 16
FRAME# 14 15 16
TSYNC1
TSSYNC
TSYNC2
TLCLK3
TLINK3
NOTE 1: TSYNC IN FRAME MODE (TCR1.1 = 0).
NOTE 2: TSYNC IN MULTIFRAME MODE (TCR1.1 = 1).
NOTE 3: TLINK IS PROGRAMMED TO SOURCE JUST THE SA4 BIT.
NOTE 4: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME.
NOTE 5: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
TCLK
CHANNEL 1
CHANNEL 2
LSB
MSB
LSB MSB
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8
TSER
TSYNC1
TSYNC2
CHANNEL 1
CHANNEL 2
D
A
B
C
D
TSIG
TCHCLK
TCHBLK3
TLCLK4
TLINK4
DON'T CARE
DON'T CARE
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BIT.
NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT
FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 6: SHOWN IS A TNAF FRAME BOUNDARY.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
