71M6543F/H and 71M6543G/GH Data Sheet
Name
Location Rst Wk Dir Description
EX_XFER
2700[0]
2700[1]
2700[2]
2700[3]
2701[7]
2700[7]
2700[6]
2700[5]
2701[6]
2701[5]
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The
bits are set by hardware and cannot be set by writing a 1. The bits are reset by writing
0. Note that if one of these interrupts is to enabled, its corresponding 8051 EX enable
bit must also be set. See 2.4.9 Interrupts, for details.
0
0
R/W
Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake the part.
This bit has no effect unless DIO4 is configured as a digital input.
EW_DIO4
28B3[2]
28B3[1]
0
0
–
–
R/W
R/W
Connects SEGDIO52 to the WAKE logic and permits SEGDIO52 rising to wake the part.
This bit has no effect unless SEGDIO52 is configured as a digital input.
EW_DIO52
Connects SEGDIO55 to the WAKE logic and permits the SEGDIO55 rising edge to
EW_DIO55
28B3[0]
0
–
R/W awaken the part. This bit has no effect unless SEGDIO55 is configured as a digital
input.
Connects PB to the WAKE logic and permits the PB rising edge to awaken the part. PB
is always configured as an input.
EW_PB
EW_RX
28B3[3]
28B3[4]
0
0
–
–
R/W
Connects RX to the WAKE logic and permits the RX rising edge to awaken the part.
See the WAKE description in 3.4 Wake on Timer for de-bounce issues.
R/W
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0]
ADC Cycles
141
00
01
10
288
384
FIR_LEN[1:0]
210C[2:1]
0
0
R/W PLL_FAST = 0:
FIR_LEN[1:0]
ADC Cycles
135
276
Not Allowed
00
01
10
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to
Table 83 on page 126 and Table 105 on page 144 for details.
v1.2
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