71M6543F/H and 71M6543G/GH Data Sheet
5.2
I/O RAM Map – Alphabetical Order
Table 71 lists I/O RAM bits and registers in alphabetical order.
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
Table 71: I/O RAM Map – Alphabetical Order
Name
Location Rst Wk Dir Description
ADC_E
2704[4]
2200[5]
0
0
0
0
R/W Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The resulting ADC and FIR clock is as shown below.
ADC_DIV
R/W
PLL_FAST = 0
6.291456 MHz
1.572864 MHz
0.786432 MHz
PLL_FAST = 1
19.660800 MHz
4.9152 MHz
MCK
ADC_DIV = 0
ADC_DIV = 1
2.4576 MHz
BCURR
2704[3]
2885[7:0]
2106[0]
0
–
0
0
–
0
R/W Connects a 100 µA load to the battery selected by TEMP_BSEL.
The result of the battery measurement.
See 2.5.7 71M6543 Battery Monitor on page 57.
BSENSE[7:0]
CE_E
R
R/W CE enable.
CE program location. The starting address for the CE program is 1024*CE_LCTN.
CE_LCTN[6:0]
(CE_LCTN[6:0], 2109[6:0] for 71M6543G, 71M6543GH)
2109[6:0] 31 31 R/W
(CE_LCTN[5:0], 2109[5:0] for 71M6543F, 71M6543H)
These bytes contain the chip identification as shown below.
CHIP_ID[15:8] CHIP_ID[7:0]
71M6543F
71M6543H
71M6543G
71M6543GH
0x04
0x04
0x05
0x05
0x10
0x11
0x10
0x11
CHIP_ID[15:8]
CHIP_ID[7:0]
2300[7:0]
2301[7:0]
0
0
0
0
R
R
104
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