71M6543F/H and 71M6543G/GH Data Sheet
Name
Location Rst Wk Dir Description
When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM.
SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if
LCD_MAP[2] and LCD_MAP[3] are cleared.
Function
DIO_EEX[1:0]
00
01
10
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
DIO_EEX[1:0]
2456[7:6]
0
–
R/W
3-Wire EEPROM interface with separate DO (SEGDIO3) and DI
(SEGDIO8) pins.
11
DIO_PV
2457[6]
2457[7]
2458[7]
2458[6]
SFR 9E
0
0
0
0
0
–
–
–
–
0
R/W Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0.
R/W Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0.
R/W Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0.
R/W Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0.
R/W Serial EEPROM interface data.
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
Serial EEPROM interface control.
Status
Bit
Read/ Reset
Write State
Name
Polarity Description
EECTRL[7:0]
SFR 9F
0
0
R/W
ERROR
BUSY
7
6
R
R
0
0
Positive 1 when an illegal command is received.
Positive 1 when serial data bus is busy.
1 indicates that the EEPROM sent an
RX_ACK
5
R
1
Positive
ACK bit.
Specifies the power equation.
Element Element Element Recommended
EQU[2:0]
Description
0
1
2
MUX Sequence
2 element, 4W,
3φ Delꢀa
2 element, 4W,
3φ Wye
3 element, 4W,
3φ ꢀye
VA(Iꢀ-IB)/
0
VC IC
IA VA IB ꢀB ꢀC VC
3
4
EQU[2:0]
2106[7:5]
0
0
R/W
VA(IA-IB)/2
VA IA
VB(IC-IB)/2
VB IB
0
IA VA IB Vꢀ Iꢀ VC
IA ꢀA IBꢀVB ICꢀV
VC ꢀC
5*
Note:
*The available CE codes implements only equation 5. Contact your local Teridian representative to obtain
CE code for equation 3 and 4.
106
© 2008–2011 Teridian Semiconductor Corporation
v1.2
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
