71M6543F/H and 71M6543G/GH Data Sheet
Name
RTC5
RTC6
RTC7
RTC8
RTC9
RTC10
RTC11
RTC12
RTC13
RTC14
TEMP
WF1
Addr
2895
2896
2897
2898
2899
289B
289C
289D
289E
289F
28A0
28B0
28B1
28B2
Bit 7
U
Bit 6
U
Bit 5
U
Bit 4
U
Bit 3
Bit 2
Bit 1
Bit 0
RTC_HR[4:0]
U
U
U
U
RTC_DAY[2:0]
U
U
U
RTC_DATE[4:0]
U
U
U
U
RTC_MO[3:0]
RTC_P[16:14]
RTC_Q[1:0]
RTC_YR[7:0]
U
U
U
U
U
RTC_P[13:6]
RTC_P[5:0]
U
U
U
RTC_TMIN[5:0]
U
TEMP_BSEL
WF_CSTART
U
U
RTC_THR[4:0]
TEMP_PWR
WF_RST
U
OSC_COMP
WF_RSTBIT
WF_TMR
WAKE_ARM
U
TEMP_BAT
WF_OVF
WF_RX
U
TBYTE_BUSY
WF_ERST
WF_PB
U
TEMP_PER[2:0]
WF_BADVDD
U
U
WF_DIO4
WF_DIO52
WF_DIO55
WF2
SLEEP
U
LCD_ONLY
U
U
EW_DIO4
U
U
EW_DIO52
U
U
EW_DIO55
U
MISC
EW_RX
U
EW_PB
U
WAKE_E 28B3
WDRST 28B4
WD_RST
TEMP_START
U
MPU PORTS
DIO_DIR[15:12]
DIO[15:12]
PORT3 SFR B0
PORT2 SFR A0
PORT1 SFR 90
PORT0 SFR 80
FLASH
DIO_DIR[11:8]
DIO_DIR[7:4]
DIO_DIR[3:0]
DIO[11:8]
DIO[7:4]
DIO[3:0]
FLSH_ERASE[7:0]
ERASE SFR 94
FLSHCTL SFR B2
FL_BANK SFR B6
PGADR SFR B7
PREBOOT
U
SECURE
U
U
U
U
FLSH_PEND FLSH_PSTWR FLSH_MEEN FLSH_PWE
FL_BANK[1:0]
U
U
U
FLSH_PGADR[5:0]
U
U
I2C
EEDATA[7:0]
EECTRL[7:0]
EEDATA SFR 9E
EECTRL SFR 9F
v1.2
© 2008–2011 Teridian Semiconductor Corporation
103
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
