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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
Name  
Location Rst Wk Dir Description  
Chop enable for the reference bandgap circuit. The value of CHOP changes on the  
rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]:  
CHOP_E[1:0]  
2106[3:2]  
0
0
R/W  
00 = toggle1 01 = positive 10 = reversed 11 = toggle  
1except at the mux sync edge at the end of an accumulation interval.  
The CHOP settings for the remote sensor.  
00 = Auto chop. Change every MUX frame.  
01 = Positive  
CHOPR[1:0]  
2709[7:6] 00 00 R/W  
10 = Negative  
11 = Auto chop (same as 00)  
DIFF0_E  
DIFF2_E  
DIFF4_E  
DIFF6_E  
210C[4]  
210C[5]  
210C[6]  
210C[7]  
0
0
0
0
0
0
0
0
R/W Enables IADC0-IADC1 differential configuration.  
R/W Enables IADC2-IADC3 differential configuration.  
R/W Enables IADC4-IADC5 differential configuration.  
R/W Enables IADC6-IADC7 differential configuration.  
Connects PB and dedicated I/O pins DIO2 through DIO11 to internal resources. If more  
than one input is connected to the same resource, the MULTIPLE column below specifies  
how they are combined.  
2455[2:0]  
2455[6:4]  
2454[2:0]  
2454[6:4]  
2453[2:0]  
2453[6:4]  
2452[2:0]  
2452[6:4]  
2451[2:0]  
2451[6:4]  
2450[2:0]  
DIO_R2[2:0]  
DIO_R3[2:0]  
DIO_R4[2:0]  
DIO_R5[2:0]  
DIO_R6[2:0]  
DIO_R7[2:0]  
DIO_R8[2:0]  
DIO_R9[2:0]  
DIO_R10[2:0]  
DIO_R11[2:0]  
DIO_RPB[2:0]  
0
0
0
0
0
0
0
0
0
0
0
Resource  
MULTIPLE  
DIO_Rx  
0
1
2
3
4
5
NONE  
R/W  
Reserved  
OR  
OR  
OR  
OR  
OR  
T0 (Timer0 clock or gate)  
T1 (Timer1 clock or gate)  
IO interrupt (int0)  
IO interrupt (int1)  
Programs the direction of the first 16 DIO pins. 1 indicates output. Ignored if the pin is  
not configured as I/O. See DIO_PV and DIO_PW for special option for DIO0 and DIO1  
R/W outputs. See DIO_EEX[1:0] for special option for SEGDIO2 and SEGDIO3. Note that  
the direction of DIO pins above 15 is set by SEGDIOx[1]. See PORT_E to avoid power-  
up spikes.  
DIO_DIR[15:12]  
DIO_DIR[11:8]  
DIO_DIR[7:4]  
DIO_DIR[3:0]  
SFR B0[7:4]  
SFR A0[7:4]  
SFR 90[7:4]  
SFR 80[7:4]  
F
F
F
F
DIO[15:12]  
DIO[11:8]  
DIO[7:4]  
DIO[3:0]  
The value on the first 16 DIO pins. Pins configured as LCD read zero. When written,  
changes data on pins configured as outputs. Pins configured as LCD or input ignore  
writes. Note that the data for DIO pins above 15 is set by SEGDIOx[0].  
SFR B0[3:0]  
SFR A0[3:0]  
SFR 90[3:0]  
SFR 80[3:0]  
R/W  
v1.2  
© 2008–2011 Teridian Semiconductor Corporation  
105  
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