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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
Name  
Location Rst Wk Dir Description  
Flash Bank Selection (71M6543G and 71M6543GH only)  
The program memory of the 71M6543G/GH consists of a fixed lower bank of 32 KB,  
addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at  
0x8000 to 0xFFFF. The I/O RAM register FL_BANK is used to switch one of four  
memory banks of 32 KB each into the address range from 0x8000 to 0xFFFF. Note that  
when FL_BANK = 0, the upper bank is the same as the lower bank.  
FL_BANK[1:0]  
SFR B6[1:0] 01 01 R/W  
Address Range for Lower Bank  
(0x0000-0x7FFF)  
0x0000-0x7FFF  
Address Range for Upper Bank  
(0x8000-0xFFFF)  
FL_BANK[1:0]  
00  
01  
10  
11  
0x0000-0x7FFF  
0x0000-0x7FFF  
0x8000-0xFFFF  
0x0000-0x7FFF  
0x0000-0x7FFF  
0x10000-0x17FFF  
0x18000-0x1FFFF  
Flash Erase Initiate  
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page  
Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the  
appropriate Erase cycle. (default = 0x00).  
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to  
FLSH_PGADR[5:0] (SFR 0xB7).  
FLSH_ERASE[7:0]  
SFR 94[7:0] 0  
0
W
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to  
FLSH_MEEN (SFR 0xB2) and the debug (CC) port must be enabled.  
Any other pattern written to FLSH_ERASE has no effect.  
Mass Erase Enable  
0 = Mass Erase disabled (default).  
1 = Mass Erase enabled.  
Must be re-written for each new Mass Erase cycle.  
FLSH_MEEN  
SFR B2[1]  
SFR B2[3]  
0
0
0
0
0
W
R
Indicates that a posted flash write is pending. If another flash write is attempted, it is  
ignored.  
FLSH_PEND  
Flash Page Erase Address  
Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle.  
(default = 0x00).  
FLSH_PGADR[5:0]  
SFR B7[7:2] 0  
W
Must be re-written for each new Page Erase cycle.  
Enables posted flash writes. When 1, and if CE_E = 1, flash write requests are stored in  
a one element deep FIFO and are executed when CE_BUSY falls. FLSH_PEND can be  
read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash writes  
are immediate.  
FLSH_PSTWR  
SFR B2[2]  
0
0
R/W  
108  
© 2008–2011 Teridian Semiconductor Corporation  
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