MV78100
Hardware Specifications
Table 20: MPP Function Summary (Continued)
MPP
Pin
0x0
0x1
0x2
0x3
0x4
0x5
0x6
MPP[14] GPIO[14]
(in/out)
SATA1_ACT
n (out)
UA1_CTSn
(in)
NAND Flash
REn[1]
(out)
TDM_
SMOSI
(out)
MPP[15] GPIO[15]
(in/out)
SATA0_ACT
n (out)
UA1_RTSn
(out)
NAND Flash
WEn[1]
(out)
TDM_
SMISO
(in)
MPP[16] GPIO[16]
(in/out)
SATA1_
PRESENTn
(out)
UA2_TXD
(out)
NAND Flash
REn[3]
(out)
TDM_
INTn
(in)
MPP[17] GPIO[17]
(in/out)
SATA0_
PRESENTn
(out)
UA2_RXD
[in)
NAND Flash
WEn[3]
(out)
TDM_
RSTn
(out)
MPP[18] GPIO[18]
(in/out)
UA0_CTSn
(in)
BOOT
NAND Flash
REn
(out)
MPP[19] GPIO[19]
(in/out)
UA0_RTSn
(out)
BOOT
NAND Flash
WEn
(out)
MPP[20] GPIO[20]
(in/out)
UA1_CTSn
(in)
TDM_
PCLK
(in/out)
MPP[21] GPIO[21]
(in/out)
UA1_RTSn
(out)
TDM_
FSYNC
(in/out)
MPP[22] GPIO[22]
(in/out)
UA3_TXD
(out)
NAND Flash
REn[2]
(out)
TDM_
DRX
(in)
MPP[23] GPIO[23]
(in/out)
UA3_RXD
(in)
NAND Flash
WEn[2]
TDM_
DTX
(out)
(out)
DEV_
AD[16]
GPIO[24]
(in/out)
UA2_TXD
(out)
TDM_
INTn
(in)
DEV_
AD[17]
GPIO[25]
(in/out)
UA2_RXD
(in)
TDM_
RSTn
(out)
DEV_
AD[18]
GPIO[26]
(in/out)
UA2_CTSn
(in)
TDM_
PCLK
(in/out)
MV-S104552-U0 Rev. D
Page 46
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
