LT3587
OPERATION
All three channels of the LT3587 use a constant frequency,
current mode control scheme to provide voltage and/or
current regulation at the output. Operation can be best un-
derstood by referring to the Block Diagram in Figure 1.
200mV, the bandgap reference, the start-up bias and the
oscillators are also turned on. The SR latch X3 is set at
the start of each oscillator cycle which turns on the power
switch Q3. Q3 turns off based on its own feedback loop,
whichconsistsoferroramplifierA5andPWMcomparator
A6. The level at the negative input of A6 is set by the error
amplifier A5, and is an amplified version of the difference
between the reference voltage of 0.8V and the maximum
If EN/SS1 is pulled higher than 200mV, the bandgap refer-
ence, the start-up bias and the oscillator are turned on. At
the start of each oscillator cycle, the SR latch X1 is set,
whichturnsonthepowerswitchQ1.Avoltageproportional
to the switch current is added to a stabilizing ramp and
the resulting sum is fed into the positive terminal of the
PWM comparator A3. When this voltage exceeds the level
atthenegativeinputofA3, theSRlatchX1isreset, turning
off the power switch Q1. The level at the negative input
of A3 is set by the error amplifier A1, which is simply an
amplified version of the difference between the reference
voltage of 1.22V and the feedback voltage. In this manner,
the error amplifier sets the correct peak switch current
level to keep the output voltage in regulation. If the error
amplifier output increases, more current is delivered to
the output; if it decreases, less current is delivered.
of the two feedback voltages at V and I . A separate
FB3
FB3
comparator (not shown) sets the maximum current limit
on Q3.
The I
pin is pulled up internally with a current that
FB3
is (1/200) times the load current out of the V
pin.
OUT3
Therefore, an external resistor connected from this pin
to ground generates a feedback voltage proportional to
the V
output load current at the I
FB3
pin. When the
FB3
OUT3
FB3
voltage at V is higher than the voltage at I , the third
channelregulatestothefeedbackvoltageatV , whichin
normal application is a divided down voltage from V
FB3
.
OUT3
In this state, the third channel behaves as a boost voltage
regulator. On the other hand if the voltage at I is higher,
FB3
Thesecondchannelisaninvertingconverter. Thischannel
is also enabled through the EN/SS1 pin. The basic opera-
tion of this second channel is the same as the positive
channel. The SR latch X2 is also set at the start of each
oscillator cycle. The power switch Q2 is turned on at the
same time as Q1. Q2 turns off based on its own feedback
loop, which consists of error amplifier A2 and PWM
comparator A4. The reference voltage of this negative
channel is ground.
the third channel regulates to the feedback voltage at I
,
FB3
which therefore regulates the V
output load current to
OUT3
a particular value. In this state, the third channel behaves
as a boost current regulator.
PMOS M1 is used as an output disconnect pass transistor
forthefirstchannel.M1disconnectstheload(V
)from
OUT1
the input as long as the voltage between CAP1 and V
IN
is less than 2.5V (typical) and the voltage between CAP1
and V is less than 10V (typ). Similarly, PMOS M3 is
OUT1
Voltage clamps (not shown) on the output of the error
amplifiers A1 and A2 enforce current limit on Q1 and Q2
respectively.
used as an output disconnect pass transistor for the third
channel. M3 disconnects the load (V ) from the input
OUT3
when the third channel is in shutdown (EN/SS3 voltage
Similar to the first channel, the third channel is also a
positive boost regulator. If EN/SS3 is pulled higher than
is lower than 200mV) and the voltage between CAP3 and
V
OUT3
is less than 10V (typical).
3587fc
9
Linear [ Linear ]
