LG Semicon
GM72V66841CT/CLT
READ to WRITE Command Interval (2)
CLK
READ
WRIT
Command
DQM,
DQMU
/DQML
2 Clock
High-Z
High-Z
CL=2
Dout
CL=3
Din
2. Same bank, different ROW address:
3. Different bank:
When the ROW address changes, consecutive
write commands cannot be executed; it is
necessary to separate the two write commands
with a Precharge command or a bank-active
command.
When the bank changes, the write can be
performed after an interval of no less than 1
cycle, provided that the other bank is in the bank-
active state. However, DQM, DQMU/DQML
must be set High so that the output buffer
becomes High-Z before data input.
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